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1 typical connection diagram load 14 13 12 11 10 9 8 1 2 3 4 5 6 7 IRS2453D vcc ct rt lo1 lo2 sd vb1 ho1 vs1 vb2 ho2 vs2 com nc + ac rectified line - ac rectified line 15v * please note that this datasheet contains advanced information which could change before the product is released to production . data sheet no. pd60259 advance informatio n IRS2453D(s)pbf self-oscillating full-bridge driver ic features integrated 600v full-bridge gate driver ? ct, rt programmable oscillator 15.6v zener clamp on vcc micropower startup logic level latched shutdown pin non-latched shutdown on ct pin (1/6th vcc) internal bootstrap fets excellent latch immunity on all inputs & outputs esd protection on all pins 14-lead soic or pdip package 1.0 usec (typ.) internal deadtime description the IRS2453D is based on the popular ir2153 self-oscillating half-bridge gate driver ic, and in corporates a high voltage full- bridge gate driver with a front end oscillator similar to the industry standard cmos 555 timer. hvic and latch immune cmos technologies enable ruggediz ed monolithic construction. the output driver features a high pulse current buffer stage designed for minimum driver cross-conduction. noise immunity is achieved with low di/dt peak of the gate drivers, and with a undervoltage lockout hysteresis greater than 1.5v. the IRS2453D also includes latched and non-latched shutdown pins. package 14 lead pdip 14 lead soic IRS2453Dpbf (narrow body) IRS2453Dspbf
2 IRS2453Dpbf absolute maximum ratings absolute maximum ratings indicate sustained limits beyond wh ich damage to the device may o ccur. all voltage parameters are absolute voltages referenced to com, all currents are defi ned positive into any lead. t he thermal resistance and power dissipation ratings are measured under board mounted and still air conditions. parameter symbol definition min. max. units v b1, v b2 high side floating supply voltage -0.3 625 v v s1, v s2 high side floating supply offset voltage v b - 25 v b + 0.3 v v ho1 , v ho2 high-side floating output voltage v s - 0.3 v b + 0.3 v v lo1 , v lo2 low-side output voltage -0.3 v cc + 0.3 v v rt r t pin voltage -0.3 v cc + 0.3 v v ct c t pin voltage -0.3 v cc + 0.3 v v sd sd pin voltage -0.3 v cc + 0.3 v i rt r t pin current -5 5 ma i cc supply current (note 1) --- 25 ma dv s /dt allowable offset voltage slew rate -50 50 v/ns p d maximum power dissipation @ t a
3 IRS2453Dpbf recommended operating conditions for proper operation the device should be used within the recommended conditions. parameter symbol definition min. max. units v bs1 , v bs2 high side floating supply voltage v cc - 0.7 v clamp v v s1 , v s2 steady state high side floating supply offset voltage -3.0 (note 2) 600 v v cc supply voltage vccuv+ v clamp v i cc supply current (note 3) 5 ma t j junction temperature -25 125 oc note 2: care should be taken to avoid output switching conditions where the v s node flies inductively below ground by more than 5v. note 3: enough current should be supplied to the v cc pin of the ic to keep the internal 15.6v zener diode clamping the voltage at this pin. recommended component values parameter symbol component min. max. units r t timing resistor value 1 --- k ?
4 IRS2453Dpbf electrical characteristics v bias (v cc , v bs ) = 14v, c t = 1 nf and t a = 25c unless otherwise specified. the v o and i o parameters are referenced to com and are applicable to the respective output leads : ho or lo. clo1=clo2=cho1=cho2=1nf. symbol definition min typ max units test conditions low voltage supply characteristics v ccuv + rising v cc undervoltage lockout threshold 10.0 11.0 12.0 v ccuv - falling v cc undervoltage lockout threshold 8.0 9.0 10.0 v v ccuvhys v cc undervoltage lockout hysteresis 1.6 2.0 2.4 i qccuv micropower startup v cc supply current --- 140 200 a v cc floating supply characteristics i qbs1uv, i qbs2uv micropower startup v bs supply current --- 3 10 a v cc oscillator i/o characteristics f osc oscillator frequency 19.6 20.2 20.8 khz r t = 36.5k ? ?
5 IRS2453Dpbf electrical characteristics v bias (v cc , v bs ) = 14v, c t = 1 nf and t a = 25c unless otherwise specified. the v o and i o parameters are referenced to com and are applicable to the respective output leads : ho or lo. clo1=clo2=cho1=cho2=1nf. symbol definition min typ max units test conditions gate driver output characteristics v oh high-level output voltage, v bias - v o --- vcc --- i o = 0a v ol low-level output voltage, v o --- com --- i o = 0a v ol_uv uv-mode output voltage, v o --- com --- i o = 0a , v cc shutdown v sd shutdown threshold at sd pin (latched) --- 2.0 --- v v ctsd c t voltage shutdown threshold (non latched) --- 2.3 --- v v rtsd sd-mode r t output voltage, v cc - v rt --- 10 50 mv i rt = 100 bootstrap fet characteristics vb1_on vb2_on vb when the bootstrap fet is on --- 13.7 --- v ib1_cap ib2_cap vb source current when fet is on 30 55 --- cbs=0.1uf ib1_10v ib2_10v vb source current when fet is on 8 12 --- ma vb=10v
6 IRS2453Dpbf lead assignment 14 13 12 11 10 9 8 1 2 3 4 5 6 7 i r s 2 4 5 3 d vcc ct rt lo1 lo2 sd vb1 ho1 vs1 vb2 ho2 vs2 com nc lead definitions lead pin symbol description 1 vcc logic and internal gate drive supply voltage 2 com ic power and signal ground 3 ct oscillator timing capacitor input 4 rt oscillator timing resistor input 5 sd shutdown input 6 lo1 low-side gate driver output 7 lo2 low-side gate driver output 8 vs2 high voltage floating supply return 9 ho2 high-side gate driver output 10 vb1 high side gate driver floating supply 11 nc no connect 12 vs1 high voltage floating supply return 13 ho1 high-side gate driver output 14 vb1 high side gate driver floating supply
7 IRS2453Dpbf functional block diagram vb1 pulse gen delay pulse filter lo1 vs1 r s q ct rt rq s q ho1 - - - + + + r r r/2 r/2 vb2 pulse gen delay hv level shift vcc pulse filter lo2 vs2 com r s q 15.4v ho2 sd 2.0v uv detect dead time s r q dead time r1 s q r2 bootstrap drive 4 3 5 2 7 1 8 9 10 6 12 13 14 hv level shift bootstrap drive q all values are typical.
8 IRS2453Dpbf timing diagram dt dt 1/3 vcc 2/3 vcc vcc vccuv+ lo1 vcc lo2 vcc 1/6 vcc vrt vcc irt -1ma 1ma vcc vcc ho1 ho2 dt fault mode vct<1/6*vcc
9 IRS2453Dpbf functional description under-voltage lock-out mode (uvlo) the under-voltage lockout mode (uvlo) is defined as the state the ic is in when vcc is below the turn-on threshold of the ic. the IRS2453D under voltage lock-out is designed to maintain an ultra low supply current of less than 150ua, and to guarantee the ic is fully functional before the high and low side output drivers are activated. during under voltage lock-out mode, the high and low-side driver outputs lo1, lo2, ho1, ho2 are all low. with vcc above the vccuv+ threshold, the ic turns on and the output begin to oscillate. normal operating mode once vcc reaches the start-up threshold vccuv+, the mosfet m1 opens, rt increases to approximately vcc (vcc- vrt+) and the external ct capacit or starts charging. once the ct voltage reaches vct- (about 1/3 of vcc), established by an internal resistor ladder, lo1 and ho2 turn on with a delay equivalent to the deadtime td. once the ct voltage reaches vct+ (approximately 2/3 of vcc), lo1 and ho2 go low, rt goes down to approximately ground (vrt-), the ct capacitor starts discharging and the deadtime ci rcuit is activated. at the end of the deadtime, lo2 and ho1 go high. once the ct voltage reaches vct-, lo2 and ho1 go low, rt goes to high again, the deadtime is activated. at the end of the deadtime, lo1 and ho2 go high and the cycle starts over again. the frequency is best determined by the graph, frequency vs. rt, page 3, for different values of ct. a first order approximate of the oscillator frequency can also be calculated by the following formula:: ct rt f
10 IRS2453Dpbf IRS2453D IRS2453Ds
11 IRS2453Dpbf order information 8-lead pdip: order IRS2453Dpbf 8-lead soicn: order IRS2453Dspbf 8-lead soicn tape & reel: order IRS2453Dstrpbf qualification: industrial, msl3, lead-free world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105 http://www.irf.com/ data and specifications subject to change without notice. 3/27/2006 lead free released non-lead free released part number date code sxxxxx yww? ?xxxx pin 1 identifier ir logo lot code (prod mode - 4 digit spn code) assembly site code per scop 200-002 p ? marking code

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